In current practice, the computer architecture of different computers allows for access of system event registers in two conflicting manners. Assuming that a system register is one word of data, four bytes long, the register can be organized with the most significant byte in the lowest memory address or the highest memory address. In a multi-byte memory block, “big endian” stores the most significant byte (MSB) in the lowest memory address, which is the address of the data. “Little endian” stores the least significant byte (LSB) in the lowest memory address, which is the address of the data.
Different processors are capable of operation in either big or little endian mode. Some processors are capable of operation in either mode, depending on the operating system, or other criteria. The boot-up firmware (BIOS) must know and define in which mode the processor is to operate. Thus, in the current practice, the firmware for a given computer must be customized to read/write memory according to the corresponding architecture, i.e., big endian or little endian.
For example, the Itanium® Processor Family, from Intel® Corporation, is endian agnostic, i.e., it can operate in either big endian or little endian mode. Itanium® processors running Microsoft™ Windows™, available from Microsoft Corporation, and Linux, available free from a number of sources, operate in little endian mode. HP-UX, available from Hewlett-Packard Company, operates in big endian mode.